Programmable logic devices such as FPGAs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of large systems often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) flow are synthesis, mapping, placement, and routing.
In semiconductor circuits such as programmable logic circuits, interconnect wires connecting two or more points on a chip typically are coupled to a driving buffer (inverter) and a receiver. The delay from the input of the driving buffer to the input of the receiver may be a function of the intrinsic delay of the driving buffer (delay without any loading), the resistance and capacitance of the interconnect wire, and the input capacitance of the receiver.
As design geometries shrink, a reduction in the spacing between wires occurs which results in increased interconnect capacitance. The wires in the programmable device also become thinner which results in an increase in interconnect resistance. Together, these factors cause the resistance and capacitance of the interconnect to play a larger role in impacting the delay from an input of the driving buffer to the input of the receiver.